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r10ds0206ej0100 rev.1.00 page 1 of 10 2014.2.27 rmlv0408e series 4mb advanced lpsram (512-kword 8-bit) description the rmlv0408e series is a family of 4-mbit static rams organized 524,288-word 8-bit, fabricated by renesas?s high-performance advanced lpsram t echnologies. the rmlv0408e series has realized higher density, higher performance and low power consumption. the rmlv0408e series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. it is of fered in 32-pin sop, 32-pin tsop (ii) or 32-pin stsop. features ? single 3v supply: 2.7v to 3.6v ? access time: 45ns (max.) ? current consumption: standby: 0.4a (typ.) ? equal access and cycle times ? common data input and output three state output ? directly ttl compatible all inputs and outputs ? battery backup operation part name information part name access time temperature range package shipping container rmlv0408egsa-4s2#aa0 45 ns -40 ~ +85c 8mm13.4mm 32-pin plastic stsop tray max. 234pcs/tray max. 1872pcs/inner box rmlv0408egsa-4s2#ka0 embossed tape 1000pcs/reel rmlv0408egsb-4s2#aa0 400-mil 32pin plastic tsop (ii) tray max. 117pcs/tray max. 936pcs/inner box rmlv0408egsb-4s2#ha0 embossed tape 1000pcs/reel rmlv0408egsp-4s2#ca0 525-mil 32-pin plastic sop tube max. 25pcs/tube max. 900pcs/inner box rmlv0408egsp-4s2#ha0 embossed tape 1000pcs/reel r10ds0206ej0100 rev.1.00 2014.2.27
rmlv0408e series r10ds0206ej0100 rev.1.00 page 2 of 10 2014.2.27 pin arrangement pin description pin name function v cc power supply v ss ground a0 to a18 address input i/o0 to i/o7 data input/output cs# chip select we# write enable oe# output enable 32-pin stsop a 11 a9 a8 a13 we# a18 a15 vcc a17 a16 a14 a12 a7 a6 a5 a4 oe# a10 cs# i/o7 i/o6 i/o5 i/o4 i/o3 vss i/o2 i/o1 i/o0 a0 a1 a2 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 (top view) (top view) 32-pin sop 32-pin tsop (ii) a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 vss v cc a15 a17 we# a13 a8 a9 a11 oe# a10 cs# i/o7 i/o6 i/o5 i/o4 i/o3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
rmlv0408e series r10ds0206ej0100 rev.1.00 page 3 of 10 2014.2.27 block diagram operation table cs# we# oe# i/o0 to i/o7 operation h x x high-z standby l h l dout read l l x din write l h h high-z output disable note 1. h: v ih l:v il x: v ih or v il absolute maximum ratings parameter symbol value unit power supply voltage relative to v ss v cc -0.5 to +4.6 v terminal voltage on any pin relative to v ss v t -0.5 *2 to v cc +0.3 *3 v power dissipation p t 0.7 w operation temperature topr -40 to +85 c storage temperature range tstg -65 to +150 c storage temperature range under bias tbias -40 to +85 c note 2. -3.0v for pulse 30ns (full width at half maximum) 3. maximum voltage is +4.6v. memory matrix a0 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 2,048 x 2,048 row decode r ? ? ? ? ? input data control a 18 a16 a15 a14 a 3 a2 a1 ? ? ? ? ? ? i/o0 i/o7 cs# we# oe# v cc v ss timing pulse generato r read/write control column i/o a17 column decode r
rmlv0408e series r10ds0206ej0100 rev.1.00 page 4 of 10 2014.2.27 dc operating conditions parameter symbol min. typ. max. unit note supply voltage v cc 2.7 3.0 3.6 v v ss 0 0 0 v input high voltage v ih 2.2 v cc +0.3 v input low voltage v il -0.3 0.6 v 4 ambient temperature range ta -40 +85 c note 4. -3.0v for pulse 30ns (full width at half maximum) dc characteristics parameter symbol min. typ. max. unit test conditions input leakage current | i li | 1 ? avin = v ss to v cc output leakage current | i lo | 1 ? a cs# = v ih or oe# =v ih or we#= v il , v i/o = v ss to v cc operating current i cc 10 ma cs# =v il , others = v ih /v il , i i/o = 0ma average operating current i cc1 20 ma cycle = 55ns, duty = 100%, i i/o = 0ma, cs# = v il , others = v ih /v il 25 ma cycle = 45ns, duty = 100%, i i/o = 0ma, cs# = v il , others = v ih /v il i cc2 2.5 ma cycle = 1 ? s, duty = 100%, i i/o = 0ma, cs# 0.2v, v ih vcc-0.2v, v il 0.2v standby current i sb 0.1 *5 0.3 ma cs# =v ih , others = v ss to v cc standby current i sb1 0.4 *5 2 ? a ~+25c vin = v ss to v cc , cs# v cc -0.2v 3 ? a ~+40c 5 ? a ~+70c 7 ? a ~+85c output high voltage v oh 2.4 v i oh = -1ma v oh2 v cc -0.2 v i oh = -0.1ma output low voltage v ol 0.4 v i ol = 2.1ma v ol2 0.2 v i ol = 0.1ma note 5. typical parameter indicates the value for the cent er of distribution at 3.0v (ta=25oc), and not 100% tested. capacitance (vcc = 2.7v ~ 3.6v, f = 1mhz, ta = -40 ~ +85c) parameter symbol min. typ. max. unit test conditions note input capacitance c in 8 pf vin =0v 6 input / output capacitance c i/o 10 pf v i/o =0v 6 note 6. this parameter is sampled and not 100% tested.
rmlv0408e series r10ds0206ej0100 rev.1.00 page 5 of 10 2014.2.27 ac characteristics test conditions (vcc = 2.7v ~ 3.6v, ta = -40 ~ +85c) ? input pulse levels: v il = 0.4v, v ih = 2.4v ? input rise and fall time: 5ns ? input and output timing reference level: 1.4v ? output load: see figures (including scope and jig) read cycle parameter symbol min. max. unit note read cycle time t rc 45 ns address access time t aa 45 ns chip select access time t acs 45 ns output enable to output valid t oe 22 ns output hold from address change t oh 10 ns chip select to output in low-z t clz 10 ns 7,8 output enable to output in low-z t olz 5 ns 7,8 chip deselect to output in high-z t chz 0 18 ns 7,8,9 output disable to output in high-z t ohz 0 18 ns 7,8,9 write cycle parameter symbol min. max. unit note write cycle time t wc 45 ns address valid to write end t aw 35 ns chip select to write end t cw 35 ns write pulse width t wp 35 ns 10 address setup time to write start t as 0 ns write recovery time from write end t wr 0 ns data to write time overlap t dw 25 ns data hold from write end t dh 0 ns output enable from write end t ow 5 ns 7 output disable to output in high-z t ohz 0 18 ns 7,9 write to output in high-z t whz 0 18 ns 7,9 note 7. this parameter is sampled and not 100% tested. 8. at any given temperat ure and voltage condition, t chz max is less than t clz min, and t ohz max is less than t olz min, for any device. 9. t chz , t ohz and t whz are defined as the time when the i/o pins enter a high-impedanc e state and are not referred to the i/o levels. 10. t wp is the interval between write start and write end. a write starts when both of cs# and we# become active a write is performed during the ov erlap of a low cs#, a low we# a write ends when any of cs#, we# becomes inactive. i/o 1.4v r l = 500 ohm c l = 30 pf
rmlv0408e series r10ds0206ej0100 rev.1.00 page 6 of 10 2014.2.27 timing waveforms read cycle note 11. t chz and t ohz are defined as the time when the i/o pins ent er a high-impedance state and are not referred to the i/o levels. 12. this parameter is sampled and not 100% tested. 13. at any given temperat ure and voltage condition, t chz max is less than t clz min, and t ohz max is less than t olz min, for any device. t aa cs# a 0~18 t oh t clz t acs t oe t olz t chz oe# i/o 0~7 t ohz high impedance t rc valid address valid data *11,12,13 *11,12,13 *12,13 *12,13 we# v ih we# = ?h? level
rmlv0408e series r10ds0206ej0100 rev.1.00 page 7 of 10 2014.2.27 write cycle (1) (we# clock, oe#=?h? while writing) note 14. t wp is the interval between write start and write end. a write starts when both of cs# and we# become active. a write is performed during the over lap of a low cs# and a low we#. a write ends when any of cs# or we# becomes inactive. 15. t ohz and t whz are defined as the time when the i/o pins ente r a high-impedance state and are not referred to the i/o levels. 16. this parameter is sampled and not 100% tested. 17. during this period, i/o pins are in the output st ate so input signals must not be applied to the i/o pins. cs# a 0~18 t cw t whz oe# we# i/o 0~7 t dh t wc valid address t wr t aw t as t wp t dw *14 *15,16 *15,16 t ohz valid data *17
rmlv0408e series r10ds0206ej0100 rev.1.00 page 8 of 10 2014.2.27 write cycle (2) (we# clock, oe# low fixed) note 18. t wp is the interval between write start and write end. a write starts when both of cs# and we# become active. a write is performed during the over lap of a low cs# and a low we#. a write ends when any of cs# or we# becomes inactive. 19. t whz is defined as the time when the i/o pins enter a high-impedance state and are not referred to the i/o levels. 20. this parameter is sampled and not 100% tested. 21. during this period, i/o pins are in the output st ate so input signals must not be applied to the i/o pins. cs# a 0~18 t cw t whz oe# we# i/o 0~7 t dh t wc valid address t wr t aw t as t wp t dw t ow *18 *19,20 valid data v il oe# = ?l? level *21 *21
rmlv0408e series r10ds0206ej0100 rev.1.00 page 9 of 10 2014.2.27 write cycle (3) (cs# clock) note 22. t wp is the interval between write start and write end. a write starts when both of cs# and we# become active. a write is performed during the over lap of a low cs# and a low we#. a write ends when any of cs# or we# becomes inactive. cs# a 0~18 t cw oe# we# i/o 0~7 t dh t wc valid address t wr t aw t as t wp t dw v ih oe# = ?h? level *22 valid data
rmlv0408e series r10ds0206ej0100 rev.1.00 page 10 of 10 2014.2.27 low v cc data retention characteristics parameter symbol min. typ. max. unit test conditions *24 v cc for data retention v dr 1.5 v vin 0v, cs# v cc -0.2v data retention current i ccdr 0.4 *23 2 ? a ~+25c v cc =3.0v, vin 0v, cs# vcc-0.2v 3 ? a ~+40c 5 ? a ~+70c 7 ? a ~+85c chip deselect time to data retention t cdr 0 ns see retention waveform. operation recovery time t r 5 ms note 23. typical parameter indicates the value for the cent er of distribution at 3.0v (ta=25oc), and not 100% tested. 24. cs# controls address buffer, we # buffer, oe# buffer, and i/o buffer. if cs# controls data re tention mode, vin levels (address, we#, oe#, i/o) can be in the high-impedance state. low vcc data retention timing waveforms (cs# controlled) cs# v cc cs# controlled t cdr t r 2.7v 2.7v 2.2v 2.2v v dr cs# v cc -0.2v
all trademarks and registered trademarks are t he property of their respective owners. revision history rmlv0408 e series data sheet rev. date description page summary 1.00 2014.2.27 first edition issued
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